The present invention relates to analog-to-digital converters in general, and to differential analog-to-digital converters in particular.
The usefulness of Analog-to-Digital Converters (ADCs) is well known. One type of ADC is known as a Successive Approximation (SSA) ADC. An SSA ADC uses a Digital-to-Analog Converter (DAC) in a feedback loop, in combination with a comparator and Successive Approximation Register (SAR). An SSA ADC first sets a Most Significant Bit (MSB) using the SAR. The comparator then compares the analog input to be converted with the DAC feedback to determine whether the input is larger or smaller than xc2xd the full scale reference voltage. If the input voltage is greater than xc2xd the reference voltage the MSB is left unchanged, otherwise it is reset to the opposite state. The analog input voltage is then reduced by the compared xc2xdreference voltage and compared with xc2xd2, or xc2xc, the reference voltage to set the next MSB. The process is continued until a desired Least Significant Bit (LSB) is set.
Traditional SSA ADCs are undesirably prone to introducing errors though, due to the inclusion of both a comparator and DAC. To address this shortcoming, differential SSA ADCs have been proposed wherein two differential inputs are provided. However, many conventional Differential SSA ADCs are relatively costly and complicated in nature. It is an object of the present invention to provide a simplfied differential SSA ADC.
A method for converting a plurality of input signals being indicative of a signal to be converted to a digital output including: setting a plurality of codes each being indicative of a corresponding reference level; and, for each one of the codes, converting the one code to a first analog signal, and summing the first analog signal with a first of the input signals to provide a first summed signal; complementing the one code to provide a complemented code, converting the complemented code to a second analog signal, and summing the second analog signal with a second of the input signals to provide a second summed signal corresponding to the first summed signal; comparing the corresponding first and second summed signals to provide a comparison signal; and, setting at least a portion of the digital output according to the comparison signal.